Advanced embedded dynamic random access memories (EDRAMs) are fabricated with lightly P− type doped substrates using triple well structures in order to form buried diffused capacitor plates and to isolate the charge transfer NFET of the EDRAM. However, the combination of lightly P-type doped substrates and triple well structures includes parasitic NPN and PNP bipolar transistors in adjacent NFETs and PFETs which can form a parasitic latch and can go into latch-up mode (high current flow with feedback) when charge pairs are generated, for example, by heavy ions striking the sources, drains or wells of adjacent NFETs and PFETs or by unanticipated voltage variations in the power supplies feeding the sources, drains or wells of adjacent NFETs and PFETs. Latch-up, when it occurs, can result in catastrophic failure of the devices in which it occurs and even regions of the integrated circuit chip containing the latched-up devices. Therefore, there is a need for triple-well CMOS device structures with increased latch-up immunity and methods of fabricating triple-well CMOS device structures with increased latch-up immunity.